1. Field of the Invention
The present invention relates to a liquid crystal display device. More particularly, the present invention relates to a liquid crystal display device and a method of driving the same, in which the transmission sequence of image data is modified to prevent a reduction in image quality.
2. Discussion of the Related Art
In general, a liquid crystal display device includes a liquid crystal panel for displaying an image signal and a drive circuit for applying drive signals to the liquid crystal panel.
Although not shown in the drawings, the liquid crystal panel is comprised of two transparent substrates (glass substrates) bonded to each other so as to have a certain space in-between, and a liquid crystal layer formed between the two transparent substrates. On one of the two transparent substrates is formed a plurality of gate lines arranged at certain regular intervals, a plurality of data lines arranged at certain regular intervals perpendicularly to the gate lines, pixel electrodes formed respectively in pixel areas defined by the gate lines and the data lines, and a plurality of thin film transistors formed in the crossing areas of the gate lines and the data lines and switched according to scan signals of the gate lines to thereby transmit pixel voltages from the data lines to the pixel electrodes, respectively. In addition, in the other substrate is formed a black matrix layer for blocking light of the remaining portions except for the pixel areas, a color filter layer for embodying color in each pixel area, and a common electrode for applying an electric field facing the pixel electrode.
Hereafter, a related art liquid crystal display (LCD) device is explained in detail, with reference to the accompanying drawings.
FIG. 1 shows a schematic configuration of a related art LCD device.
As shown in FIG. 1, the related art LCD device includes a liquid crystal panel 120 having a plurality of gate lines GL arranged in one direction, and a plurality of data lines DL arranged in one direction so as to cross perpendicularly to the gate lines GL. Here, the liquid crystal panel 120 is divided into a display section 100 for displaying a real image and a non-display section 110 to which drive ICs are connected. In addition, the display section 100 is divided into a first display section 100a and a second display section 100b by a specific data line 160 (hereinafter, referred to as a “reference data line 160”) among the data lines DL.
In addition, the related art LCD device includes a plurality of first to third data drive ICs DD1, DD2, and DD3 arranged to the left of the reference data line 160 and serving to drive the data lines DL of the first display section 100a, a plurality of fourth to sixth data drive ICs DD4, DD5, and DD6 arranged to the right of the reference data line 160 and serving to drive the data lines DL of the second display section 100b, and a timing controller 141 for receiving a plurality of image data sequentially output from the system (not shown) and rearranging them into a plurality of first image data Data1 and a plurality of second image data Data2. At this time, the timing controller inputs the plurality of the first image data Data1 into the data drive ICs DD1, DD2 and DD3 of the first display section in sequence, i.e., from the first data drive IC DD1 farthest from the reference data line 160 to the third data drive IC DD3 closest to the reference data line 160. Furthermore, the timing controller inputs the plurality of the second image data Data2 into the data drive ICs DD4, DD5 and DD6 of the second display section in sequence, i.e., from the fourth data data drive IC DD4 closest to the reference data line 160 to the sixth data drive IC DD6 farthest from the reference data line 160. In addition, the timing controller 141 supplies various control signals required for each of the gate drive ICs GD through an FPC 180 and a gate TCP 133. On the other hand, although not shown in the drawings, the timing controller 141 is further provided Here, each gate drive IC GD is mounted on each gate TCP (tape carrier package) 133, and the gate TCP 133 connects the liquid crystal panel 120 with a gate printed circuit board 130. The respective data drive ICs DD1 to DD6 are mounted on the respective data TCPs 143, and the data TCP 143 connects the liquid crystal panel 120 with a data printed circuit board (PCB) 140. The gate PCB 130 and the data PCB 140 are interconnected through the flexible printed circuit (FPC) 180. Here, the timing controller 141 is mounted on the data PCB 140.
In addition, between the timing controller 141 and the first to third data drive ICs DD1, DD2 and DD3 is formed a first data transmission line 142a. A second data transmission line 142b is formed between the timing controller 141 and the fourth to sixth data drive ICs DD4 to DD6. Here, the first data transmission line 142a functions to transmit the first image data Data1 from the timing controller 141 to the first to third drive ICs DD1 to DD3. The second data transmission line 142b functions to transmit the second image data Data2 to the fourth to sixth data drive ICs DD4 to DD6.
In this way, the timing controller 141 bisects the number of image data to be displayed on a single horizontal line of the liquid crystal panel 120, i.e., divides the plurality of image data into a plurality of first image data Data1 and a plurality of second image data Data2. Also, the timing controller 141 applies the plurality of the first image data Data1 to the first to third data drive ICs DD1 to DD3 in sequence, and simultaneously applies the plurality of the second image data Data2 to the fourth to sixth data drive ICs DD4 to DD6.
The operation of the above-constructed related art LCD device will be explained below.
FIG. 2 explains the sequence of inputting the first and second image data to each data drive IC by means of the timing controller of FIG. 1.
First, the timing controller 141 receives R, G, B image data from the system and rearranges the R, G, B image data into first image data Data1 and second image data Data2, which are output at the same time. As shown in FIG. 2, the timing controller 141 inputs the first image data Data1 to the first to third data drive ICs DD1 to DD3 in sequence, i.e., from the first data drive IC DD1 farthest from the reference data line 160 to the third data drive IC DD3 closest to the reference data line 160 (the first direction in FIG. 2). At the same time, the timing controller 141 inputs the second image data Data2 to the fourth to sixth data drive ICs DD4 to DD6 in sequence, i.e., from the fourth data drive IC DD4 nearest to the reference data line 160 to the sixth data drive IC DD5 farthest from the reference data line 160 (the second direction in FIG. 2).
That is, first, the first image data Data1 is input to the first data drive IC DD1, and at the same time the second image data Data2 is input to the fourth data drive IC DD4. Then, the first image data Data1 is input to the second data drive IC DD2, and simultaneously the second image data Data2 is input to the fifth data drive IC DD5. Finally, the first image data Data1 is input to the third data drive IC DD3, and at the same time the second image data Data2 is input to the sixth data drive IC DD6.
In addition, as shown in FIG. 2, the timing controller 141 may supply the first image data Data1 in a third direction, and may supply the second image data Data2 in a fourth direction. That is, the timing controller 141 may input the first image data Data1 to the data drive ICs DD1 to DD3 sequentially, i.e., from the third data drive IC DD3 nearest to the reference data line 160 to the first data drive IC DD1 farthest from the reference data line 160 (the third direction of FIG. 2). At the same time, the timing controller 141 may input the second image data Data2 to the data drive ICs DD4 to DD6 sequentially, i.e., from the sixth data drive IC DD6 farthest from to the reference data line 160 to the fourth data drive IC DD4 nearest to the reference data line 160 (the fourth direction of FIG. 2).
In the LCD device having the above construction, if the total number of the output pins of the data drive ICs DD1 to DD6 does not match that of the whole data lines DL, the following problem occurs.
Generally, the data drive ICs DD1 to DD6 each have 642 output pins. As described above, thus, six data drive ICs DD1 to DD6 have a total of 3852 output pins (642×6). In addition, when the liquid crystal panel 120 has an XGA resolution (1280×768), the total number of data lines thereof becomes 3840 (1280×3(R,G,B)). Here, the total number (3852) of the output pins of the data drive ICs DD1 to DD6 does not exactly match that (3840) of the data lines DL. Thus, the data drive ICs DD1 to DD6 have a certain number of dummy output pins, i.e., twelve dummy output pins (the total number of output pins (3852)−the number of data lines (3840)=12).
Here, the timing controller 141 bisects 3840 image data corresponding to the total number of the data lines DL, such that the 1920 first image data Data1 are supplied to a first data drive IC group 200a and the remaining 1920 second image data Data2 are supplied to a second data drive IC group 200b. Thus, the above twelve dummy output pins are divided into six dummy output pins in the first data drive IC group 200a and six dummy output pins in the second data drive IC group 200b. 
The above problem will be more specifically described below.
FIG. 3 shows the connection between the output pins of the data drive ICs and the data lines, and FIG. 4 shows the brightness difference between pixel areas in the central portion of a related art liquid crystal panel.
Here, for convenience of explanation, as shown in FIG. 3, it is assumed that each data drive IC DD1 to DD6 has five output pins N1 to N5, and the total number of the data lines DL is twenty six, which is four less than the total number (30) of output pins. Then, the timing controller 141 bisects the 26 image data corresponding to the total number (26) of data lines DL, and thirteen first image data Data1 are supplied to the first data drive IC group 200a and the remaining thirteen second image data Data2 are supplied to the second data drive IC group 200b. 
Here, the first image data Data1 output from the timing controller 141 is filled in the first to third data drive ICs DD1 to DD3 sequentially in the first direction. The second image data Data2 are filled sequentially in the fourth to sixth data drive ICs DD4 to DD6 in the second direction. Thus, the first and second data drive ICs DD1 and DD2 and the fourth and fifth data drive ICs DD4 and DD5 are filled respectively with the first and second image data as much as the number (5) of their own output pins N1 to N5. However, the third data drive IC DD3, which is the last to be filled with the first image data Data1 in the firstdata drive IC group 200a, is filled with the first image data Data1 corresponding to three output pins N1 to N3. Similarly, the sixth data drive IC DD6, which is the last to be filled with the second image data Data2 in the second data drive IC group 200b, is filled with the second image data Data2 corresponding to three output pins N1 to N3. Therefore, in the third data drive IC DD3 and the sixth data drive IC DD4, respectively, the fourth and fifth output pins N4 and N5 among the five output pins N1 to N5 are left as a dummy output pin.
Here, the fourth and fifth output pin N4 and N5 are not connected with the data line DL. Thus, the data lines DL, which are connected to the third output pin N3 of the third data drive IC DD3 and the first output pin N1 of the fourth data drive IC DD4 are adjacent to each other. Since the spacing between the output pins N1 to N5 provided in each data drive IC DD1 to DD6 differs from that of the data lines DL, link lines L1 to L5 connecting the output pins N1 to N5 of the data drive ICs DD1 to DD6 with the data lines DL have a fan-like shape. Accordingly, the third link line L3 and the first, second, fourth and fifth link lines L1, L2, L4, and L5 have a difference in their lengths. That is, the central third link line L3 is the shortest, and the farther the link line is from the central third link line, the longer it is. In other words, the central third link line L3 is the shortest. The second and fourth link lines L2 and L4 adjacent to the left and right thereof are longer than the central third one. The outermost first and fifth link lines L1 and L5 are longer than the second and fourth link lines L2 and L4.
Here, the link lines are symmetric to each other about the third link line L3 have an identical length. That is, the second and fourth link lines L2 and L4 have the same length, and the first and fifth link lines L1 and L5 have the same length.
In a case where different link lines L1 to L5 have different lengths, the link lines L1 to L5 may have different resistances. In order to avoid this, the central third data line L3 may take a serpentine form so as to have plural curvatures, not a straight form. These curvatures are formed most in the central third link line L3, and the farther a link line is from the third link line, the less curvatures it has. Thus, all the link lines L1 to L5 have almost the same length, thereby minimizing the difference in their resistance.
However, each link line L1 to L5 cannot have exactly the same length. Thus, a slight difference occurs between the resistances of the respective link lines L1 to L5. Here, because the third data drive IC DD3 has a dummy output pin, a large resistance difference occurs between the third link line L3 connected to the third output pin N3 in the third data drive IC DD3 and the first link line L1 connected to the first output pin N1 in the fourth data drive IC DD4. More specific details thereon will be described below.
That is, assume that a difference occurs in the resistance between the link lines L1 to L5 connected to each output pin N1 to N5 in the third and fourth drive ICs DD3 and DD4. Specifically, it is assumed that the third link line L3 has a resistance value of 100, the second and fourth link lines L2 and L4 have an identical resistance value of 101, and the first and fifth link lines L1 and L5 have the same resistance value of 102. Here, the reason why the first link line L1 and the fifth link line L5 have the same resistance value is that they are placed symmetric to each other. For the same reason as above, the second link line L2 and the fourth link line L4 have the same resistance value.
Here, the forth and fifth output pins N4 and N5 of the third data drive IC DD3 are dummy output pins, and thus the fourth and fifth link lines L4 and L5 are not present.
A resistance difference of one occurs between neighboring link lines. However, since the fourth and fifth link lines L4 and L5 are not present in the third data drive IC DD3, the third link line L3 of the third data drive IC DD3 and the first link line L1 of the fourth data drive IC DD4 are adjacent to each other. Consequently, the data line DL connected to the third link line L3 of the third drive IC DD3 is placed adjacent to that connected to the first link line L1 of the fourth data drive IC DD4. Here, since the resistance value of the third link line L3 of the third data drive IC DD3 is 100, and the resistance value of the first link line L1 of the fourth data drive IC DD4 is 102, the resistance difference between the third link line L3 of the third data drive IC DD3 and the first link line L1 of the fourth data drive IC DD4 becomes larger than those of other neighboring link lines. Thus, a large voltage difference occurs between the first image data Data1, which is applied to the data line connected to the third link line L3 in the third data drive IC DD3, and the second image data Data2, which is applied to the data line connected to the first link line L1 in the fourth data drive IC DD4.
As shown in FIG. 4, an increased difference in brightness occurs between pixel areas A disposed along the data line, which is connected to the third link line N2 in the third data drive IC DD3, and pixel areas B disposed along the data line, which is connected to the first link line in the fourth data drive IC DD4, thus degrading image quality. Here, since the pixel areas A and B are placed in the central region of the display section 100 in the liquid crystal panel 120, the above difference in brightness is extremely prominent.
On the other hand, as shown in FIG. 2, if the first image data Data1 and the second image data Data2 are applied to each data drive ICs DD1 to DD6 along the third and fourth directions, dummy output pins are formed in the first data drive IC DD1, in which the first image data Data1 is filled last within the first data drive IC group 220a, and the fourth data drive IC DD4, in which the second image data Data2 is filled last within the second data drive IC group 200b. In this case, the data line DL, which is connected to the third link line L3 of the fourth data drive IC DD4, and the data line, which is connected to the fifth link line L5 of the third data drive IC DD3, are positioned adjacent to each other. Thus, similar to the case where the image data is transmitted along the first and second directions, the central region of the display section 110 in the liquid crystal panel 120 has a degraded image quality.